Abstract  

Ball grid array devices (BGAs) are widely used in a vast range of products including consumer, telecommunications and office-based systems. As an area array device of solder joints, it provides high packing density with a relatively easy introduction cycle. However, over the last couple of years, engineers have started to experiment and, in some cases, implement stacked packages, of the type often called Package on Package (PoP). In simple terms, PoP devices are the stacking of components, one on top of the other, either during the original component manufacture or during printed board assembly. Such packages, allow substantially enhanced functionality, but within the same footprint of a single BGA. PoP packaging may include direct soldering, wire bonding or conductive adhesives for device to device interconnection.

The main industry problems associated with PoP technology are open joints, warping of the two levels of component substrate and, of course, issues with the underlying PCB. Reworking these stacked components, or just the top mounted part, can be challenging and when you inspect them using 2-D X-ray inspection the data can become difficult to interpret because of the multiple levels of ball interconnection and wire-bonding that may occur within the package.

This paper will outline the process associated with soldering stacked packages using dip flux and dip solder paste that are specifically designed to overcome the incidence of package warp. Based on the process issues involved, inspection results will be presented to better illustrate the challenges in implementing PoP, or stacked packages, into production.

Introduction  

BGA and chip scale packages (CSPs) have become ever more widely used in a vast range of electronic products. Their area array of interconnections provides high packing density, yet is relatively easy to implement into production using existing assembly equipment. Developing from this, in recent years there have been experiments and, in some cases, implementation of stacking of these packages into what are often called PoP devices. For example, cell phone manufacturers have been using a PoP device with two stacked levels that contains a total of four silicon die.

As a simple definition, a POP device represents the stacking of area array components, one on top of the other, either during the original components' manufacture, or during PCB assembly. For example, rather than placing a logic device with one, or more, memory devices adjacent to each other on the board, stacking these items takes up less surface real estate, but does so with some increase in height. However, advanced package and silicon design now allow the building blocks of the PoP to be thinner using wafer thinning and flip chip interconnection. In addition, should the PoP combination be created during PCB assembly then it offers additional flexibility as to the functional capability of the same product. For example, it allows the board assembler to be able to add different sizes of memory module to the same logic device at the point of manufacture. JEDEC standard outlines exist [1] for both lower (attachment to the board) and upper package levels of a PoP with both 12 mm x 12 mm and 14 mm x 14 mm becoming popular sizes in the industry, all be it with smaller footprint devices becoming available through demand by system designers.